Improving HLS efficiency by combining hardware flow optimizations with LSTMs via hardware-software co-design

Abstract

The translation of C programs to Verilog can present significant challenges for programmers aiming to synthesize hardware. To address these challenges, several High-Level Synthesis (HLS) tools have been developed, focusing on minimizing human efforts. In this research paper, we conduct an extensive study to gain a comprehensive understanding of the HLS landscape, with a particular emphasis on evaluating the performance of LegUp, a popular open-source HLS tool. Moreover, we explore the possibilities of hardware-specific optimizations within the HLS flow to enhance area utilization and run-time efficiency. To achieve this, we augment LegUp’s static range analysis with dynamic range analysis, resulting in reduced FPGA area usage. Additionally, we demonstrate the benefits of combining bit-width optimization and operation chaining, leading to a decrease in the number of FPGA slices required. Expanding our investigation, we delve into hardware-software co-design, showcasing the positive impact of cache miss event-based profiling and cache pre-fetching on overall system performance. Through this research, we aim to provide valuable insights into the capabilities and potential enhancements of LegUp while offering novel approaches for optimizing hardware synthesis and co-design processes.